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... and to do it, as well as motion tracking and environmental feature identification, in real-time with as little latency as possible, and do it on batteries.

I keep feeling like watching the Longhorn demo at PDC 2003...



They added the third chip, besides CPU and GPU, they call it HPU (holographic processing unit), which could speed things considerably. If they hooked it directly to ccd then they could really grok terabytes of data on battery.


Magic is not possible. Whatever the HPU does is still constrained by physics. They can't explain away the engineering problem with an invented new name for a device we know nothing about except that it defies the laws of physics WRT computation.


What we do know is that fixed function ASICs can be can be 10s to 100s of times more power efficient than general purpose (Von Newman) computing.

So noting they have described defies the laws of physics.


So, where would the terabytes per second come from? ... on a head-mounted device?




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