Many ARM chips have this. | Hacker News

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		garmaine on May 9, 2019 \| parent \| context \| favorite \| on: For Better Computing, Liberate CPUs from Garbage C... Many ARM chips have this.

stcredzero on May 9, 2019 [–]

Any useful links? What are the terms I should search for?

garmaine on May 9, 2019 | [–]

It’s called a “weak ordering memory model.” Synchronization requires explicit memory fence instructions.

RISC-V, btw, supports both weak and strong memory models as an implementation choice.

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